The invention relates to test pattern generators for logic circuits.
Logic circuits for data processing and other apparatus typically consist of a network of interconnected logic gates, such as "AND" gates, "OR" gates, "NAND" gates, "NOR" gates, "NOT" gates, "XOR" gates, and so on. The network of gates has a number of inputs for receiving digits, and has a number of outputs for outputting digits. The logic circuit is designed such that for each input digit pattern, of a set of one or more input digit patterns, provided at the inputs of the network, a corresponding predetermined output digit pattern is produced at the outputs of the network.
If there is a fault or defect in the logic circuit, then for one or more input digit patterns provided at the inputs of the network, the observed output digit patterns produced at the outputs of the network will differ from the expected predetermined output digit patterns.
One way to test for faults in a logic circuit is to apply each possible input digit pattern at the inputs of the logic network, and to compare the actual output digit pattern with the expected output digit pattern. For small numbers of possible input digit patterns, the cost of storing the expected output digit patterns and performing this deterministic testing is reasonable. However, for large numbers of possible input digit patterns, the cost of such deterministic testing is too high.
An alternative method of testing for faults in a logic circuit is to apply random input digit test patterns at the inputs of the logic network, and to compare the actual output digit patterns with the expected output digit patterns. The number of random test patterns needed to achieve a selected level of confidence that a logic circuit contains no faults depends on the set of input digit patterns for which the logic circuit is designed.
Therefore, another alternative method of testing for faults in a logic circuit is to apply one or more weighted random input digit test patterns at the inputs of a logic network, and to compare the actual output digit patterns with the expected output digit patterns. In a weighted random input digit test pattern, there is at least one digit for which the probability of occurrence of one value is different from 1/N, where N is the number of different possible values of the digit. For example, for a binary digit having one of N=2 values (either "1" or "0"), in a weighted random input digit test pattern the probability of occurrence of "1" is P(1)=W(1/2), and the probability of occurrence of "0" is P(0)=1-W(1/2), where the weight W is any positive number other than one.
The weights W may be uniform across all digits in the test pattern, or the weights may be nonuniform. The weighted random test patterns are selected to achieve, efficiently and at low cost, a desired level of confidence that the logic circuit contains no faults. Weighted random testing can significantly decrease the number of test patterns which must be applied to a logic circuit to obtain the same test effectiveness as an unweighted random test.